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MRF89XA
3.4.11
BIT SYNCHRONIZER
The Bit Synchronizer (BitSync) block provides a clean
and synchronized digital output that is free of glitches.
Figure 3-13 illustrates the BitSync block output when a
Raw Demodulator FSK or OOK output is fed to it.
FIGURE 3-13:
BitSync BLOCK OUTPUT SIGNALS
Raw demodulator
output
(FSK or OOK)
DATA
BitSync Output
To DATA pin and
DCLK in
Continuous mode
DCLK
IRQ1
NumberOfBits = 1 --- -----------
The BitSync can be disabled by setting the BSYNCEN
bit (SYNCREG<6>) to ‘ 1 ’ and by holding the IRQ1 pin
(pin 22) low. However, for optimum receiver perfor-
mance, it has to be used when the device is running in
Continuous mode. With this option a DCLK signal is
present on the IRQ1 pin.
The BitSync is automatically activated in Buffered and
Packet modes. The bit synchronizer bit-rate is con-
trolled by the BRVAL<6:0> bits (BRSREG<6:0>). For a
given bit rate, this parameter is determined by
Equation 3-16 .
EQUATION 3-16:
that the BitSync can withstand. It can be esti-
mated as given in Equation 3-17 .
EQUATION 3-17:
? BR
2 Δ BR
This implies approximately six consecutive unbalanced
bytes when the Bit Rate precision is 1%, which is easily
achievable (crystal tolerance is or should be at least in
the range of 50 to 100 ppm).
f xtal
? [ 1 + val ( BRVAL<6:0> ) ]
BR = ----------------------------------------------------------------------
64
3.4.12
ALTERNATIVE SETTINGS FOR
BITSYNC AND ACTIVE FILTER
Bit Synchronizer and Active channel filter settings are
For proper operation, the Bit Synchronizer must first
receive three bytes of alternating logic value preamble,
(that is, ‘ 0101 ’ sequences). After this start-up phase,
the rising edge of the DCLK signal is centered on the
demodulated bit. Subsequent data transitions will
preserve this centering. This has two implications:
? If the bit rates of Transmitter and Receiver are
known to be the same, the MRF89XA will be able
to receive an infinite unbalanced sequence (all
‘ 0 ’s or all ‘ 1 ’s) with no restriction.
? If there is a difference in bit rate between TX and
RX, the amount of adjacent bits at the same level
a function of the reference oscillator crystal frequency,
f xtal . Settings other than those programmable with a
12.8 MHz crystal can be obtained by selecting the cor-
rect reference oscillator frequency.
? 2010–2011 Microchip Technology Inc.
Preliminary
DS70622C-page 69
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